The FP4 floating-point format with E2M1 configuration addresses memory and energy constraints of large neural networks by reducing precision to 4 bits while retaining dynamic range.

John D. Cook documented all 16 values in the signed E2M1 FP4 format, showing representations from ±0, ±0.5 to ±6 with bias of 1 and subnormals at exponent zero (https://www.johndcook.com/blog/2026/04/17/fp4/). NVIDIA hardware implements this MXFP4_E2M1 variant as part of microscaling formats introduced for Hopper and Blackwell architectures to accelerate inference (NVIDIA Blackwell Technical Overview, 2024). The pychop library reproduces these encodings for developer validation.

Related work in the QLoRA paper demonstrated 4-bit NormalFloat quantization allows fine-tuning of 65-billion parameter models on consumer GPUs by combining quantization with paging optimizers (Dettmers et al., arXiv:2305.14314, 2023). Primary source coverage centered on numerical layout and bias effects but did not connect FP4 adoption to measured reductions in memory bandwidth for transformer inference on edge hardware. Patterns from FP32 to FP16 to FP8 show consistent industry movement toward lower precision formats optimized for matrix multiplication units rather than general computation.

OCP Microscaling Formats specification formalizes FP4 alongside INT4 variants to standardize data movement between compute tiles, directly mitigating the quadratic growth in energy costs observed in models exceeding 100 billion parameters.