12 nm FinFETs Retain Gate Control to 10 mK with 24.8 mV/dec Subthreshold Floor

The study performed DC and RF measurements on regular-Vt n- and p-FinFETs across 292 K to 10 mK using a dilution refrigerator and fixed-current gm extraction at 3.26 µA/µm to bypass series resistance. This yielded continuous parameter sets injected into a BSIM-CMG framework that preserves room-temperature PDK accuracy while matching cryogenic data. The n-device shows clear velocity saturation persistence and no freeze-out, confirming CMOS viability for on-chip qubit pulse generation.

Prior cryo-CMOS work focused on 28 nm or larger nodes and discrete parameter fits at isolated temperatures, missing the continuous 1.36–292 K bridge required for co-design with superconducting qubits. The 12 nm results close that gap by demonstrating sub-30 mV/dec slopes and dynamic parameter injection that avoids re-qualification overhead. This directly supports scalable control electronics colocated with qubits, reducing interconnect heat load.

The key limitation remains the small sample size and single foundry process; statistical variation across wafers and the impact of radiation-induced traps at millikelvin are unquantified. A multi-wafer, multi-foundry replication with full S-parameter de-embedding to 20 GHz would strengthen claims for commercial quantum control ASICs.