PICasso reaches 92.7% structural Spec@3 and cuts mean insertion loss to 3.25 dB on PIC-Set

PICasso implements a constrained NL-YAML-GDS flow that injects PDK rules, runs automated P&R, enforces DRC/LVS, and closes the loop with SAX photonic simulation. The system converts natural-language specs into manufacturable layouts for both primitive devices and multi-component circuits. On the new PIC-Set benchmark it raises end-to-end specification satisfaction well above vanilla LLM baselines while producing layouts whose runtimes remain competitive with manual GUI flows.

Across the 36-task suite, structural Spec@3 peaks at 92.7% and functional Spec@3 reaches 52% on high-complexity circuits. Simulation-guided optimization lowers mean insertion loss by 1.74 dB. These gains stem from explicit domain constraints and iterative verification rather than scale alone; the paper shows that removing any single verification stage drops functional success below 30%.

Prior inverse-design literature focused on gradient-based optimization of fixed topologies; PICasso instead treats the LLM as a layout agent inside a full tape-out loop. This exposes a gap in current EDA coverage for photonic netlists that lack electrical-equivalent LVS equivalents. Deployment data from foundry PDKs will determine whether the 1.74 dB loss reduction survives process variation and whether runtime scales past the current 36-task set.

Next steps include extension of PIC-Set to 100+ tasks and integration with commercial MPW shuttles to measure yield against hand-tuned references.