China's CXMT Advances Bonded DRAM Pilot as Tech Gap with Korea Narrows Amid Export Controls

Chinese DRAM maker ChangXin Memory Technologies (CXMT) is testing a pilot production line for next-generation bonded DRAM at its Hefei facility, according to reports citing Korean media. This wafer-to-wafer hybrid bonding approach separates the memory cell array and peripheral circuitry, enabling high-density production using only DUV lithography and multi-patterning rather than restricted EUV tools.

Corroborating coverage from Wccftech and industry observers highlights CXMT's R&D push to commercialize the technology ahead of Samsung's B1b project and SK Hynix efforts, with some assessments suggesting an edge in development speed. Reuters has documented CXMT's capacity expansion to around 300,000 wafers per month across Hefei and Beijing fabs, alongside a major $3 billion supply deal with Tencent and plans for a new Shanghai DRAM plant ahead of a potential Shanghai IPO.

The patent landscape provides further context. ZDNet Korea and KnowMade data cited by TrendForce show YMTC holding 119 hybrid bonding patents (2017–early 2024) versus Samsung's 83 and SK Hynix's 11, leading to reported licensing agreements where Samsung adopts YMTC's Xtacking technology for next-generation NAND. SemiAnalysis notes CXMT's capacity share growth and state-backed supply-chain clustering in Hefei as factors accelerating its trajectory.

Wikipedia and Reuters reports place CXMT's global DRAM share at approximately 4% in mid-2025, with ongoing ramps suggesting continued momentum into 2026 despite US export controls. Seoul-based analysts and professors quoted in Korean outlets frame this as a structural challenge to Korean dominance, emphasizing the need for accelerated innovation in HBM and advanced packaging.

These developments underscore accelerating tech decoupling: China is leveraging hybrid bonding and DUV workarounds to mitigate lithography restrictions, while Korean firms face IP dependencies. Mainstream coverage has focused more on capacity deals than the specific bonded DRAM timeline, potentially understating supply-chain reconfiguration risks for global memory markets.