CMOS Bulk Terminal Yields Single-Device Spiking Neuron at 180 nm

Lab tests on commercial 180 nm CMOS dies showed the bulk terminal, normally grounded, produces subthreshold oscillations when biased above 0.4 V. These oscillations match Hodgkin-Huxley dynamics with measured spike widths of 2-5 ms and energy per spike below 1 pJ. The same device exhibits conductance modulation under repeated gate pulses, confirming dual neuron-synapse function without added capacitors.

Prior neuromorphic CMOS work, such as IBM TrueNorth's 5.4 billion transistors for one million neurons, is limited by area. The single-transistor approach reduces that count by three orders of magnitude while remaining inside standard process flows. Measured leakage stays under 10 nA per device at 0.6 V supply, directly addressing the 1000 W GPU baseline cited in the source.

The discovery aligns with Intel Loihi 2's shift toward analog-mixed-signal cores but bypasses the need for specialized foundry options. Operational deployment hinges on array-level variability below 5 percent sigma, a threshold already met in the reported 180 nm test structures.

Next steps require tape-out of a 256 by 256 array on a 22 nm node to quantify system-level power at MNIST-scale workloads against Loihi 2 reference numbers.