This arXiv preprint details fabrication of bottom-gate TiO2 ferroelectric field-effect transistors using HfZrO2 as the gate dielectric, with devices tested across two gate-stack thicknesses and varied source-drain and gate lengths. Electrical measurements report on/off ratios reaching 10^7, off-state leakage below 10^-12 A, memory windows of 3-8 V, and stable cycling, positioning the work as a hardware step toward synaptic emulation in neuromorphic circuits. As a 2026 preprint rather than peer-reviewed publication, the study relies on standard cleanroom deposition and lithography on limited prototype dies without disclosed wafer-scale statistics or full-array integration data. Prior HfZrO2 ferroelectric research, including 2019-2022 studies on doped hafnia films for non-volatile memory, established the material's CMOS compatibility and polarization retention but often overlooked TiO2 channel interfaces that here appear to boost on-current drive. Earlier neuromorphic FeFET demonstrations, such as those exploring HZO on silicon channels, typically emphasized synaptic weight updates yet reported higher leakage or narrower windows than the 3-8 V range shown; this TiO2 variant may therefore close a performance gap for analog conductance states while still facing unaddressed challenges in endurance beyond lab cycling and thermal stability during back-end integration. At a time when AI training energy costs dominate headlines, these metrics suggest a route to sub-fJ per synaptic operation if array-level parasitics can be controlled.