arXiv Review Maps Layered Error Suppression for NISQ-to-FTQC Transition

The review positions error suppression, mitigation, and partial correction as a single stack rather than isolated tools. Hardware-level dynamical decoupling and pulse shaping cut coherent errors before circuits run, while classical post-processing such as zero-noise extrapolation and probabilistic error cancellation handle residual noise. Shen emphasizes that these techniques must be co-designed with emerging syndrome-extraction circuits so that mitigation overhead does not erase the gains from early logical qubits.

Existing experimental demonstrations already show the payoff. IBM's 2023 distance-3 surface-code runs and Quantinuum's 2024 logical-qubit experiments both relied on readout-error mitigation and Clifford twirling to reach below-threshold logical error rates. The review notes that these successes were possible only because mitigation was applied after, not instead of, basic encoding. Purely software approaches without hardware co-design hit diminishing returns once logical error rates fall below 10^-3.

A key gap the paper identifies is the absence of unified benchmarks that quantify total resource cost when mitigation and correction run together. Most current metrics report only physical or only logical error rates. Shen argues that a combined figure of merit, logical error per corrected logical gate including mitigation shots, is required before hardware teams can decide optimal layer allocation.

Next steps include embedding these workflows into open-source stacks such as Qiskit and Cirq so that circuit compilers automatically insert suppression sequences and mitigation calibrations. If adopted, the framework could extend useful simulation lifetimes of 100-1000 qubit devices by 2-3 years before full fault tolerance arrives.