Planar LDPC Codes Deliver [[323,14,15]] Parameters Using Only Nearest-Neighbor iSWAP Gates on Superconducting Grids

The arXiv preprint details a family of tile-based LDPC codes whose stabilizer supports are generated on-the-fly by iSWAP walks between data and ancilla qubits. This dynamic connectivity replaces the long-range edges that have blocked prior high-rate LDPC constructions on superconducting hardware. Finite instances such as the [[323,14,15]] code operate at roughly 30 physical qubits per logical qubit and show up to 1000-fold reduction in logical error per round versus equivalent surface-code patches in circuit-level simulations.

Superconducting platforms from IBM and Google remain limited by nearest-neighbor connectivity and leakage accumulation. The new construction solves both by swapping the roles of check and data qubits each round, automatically removing leakage without dedicated reset hardware. Earlier LDPC proposals either assumed shuttling or non-planar couplers; this work demonstrates that the overhead advantage survives strict planar compilation, directly addressing the error-correction bottleneck that has kept logical qubit counts below ten in current devices.

The main limitation is that all performance figures remain numerical; no experimental implementation on hardware has been reported. A natural strengthening would be a 100-qubit superconducting demonstration measuring logical error rates below the physical rate within two syndrome rounds. Such an experiment would immediately shift roadmap priorities at multiple hardware groups toward LDPC tiling rather than surface-code scaling.