Perimeter-Gated SPADs Cut Dark Noise, Improving Direct ToF Jitter by Up to 30% in 0.35μm CMOS

The paper from Md Sakibur Sajal presents a framework separating system, circuit, and device jitter sources, then measures a counter-based TDC paired with pg-SPAD detectors. Experimental histograms show lower timing spread when perimeter gating suppresses peripheral avalanche probability, directly lowering the dominant device-level uncertainty term. Sample size is modest—single-device characterization across bias and gating conditions—yet the result is reproducible in both operating regimes.

Existing SPAD LiDAR papers have focused on quenching circuits or process scaling; this work instead exploits layout geometry already compatible with foundry CMOS. That choice matters because it avoids the cost and yield penalties of custom processes, a pattern seen in earlier perimeter-gated avalanche photodiode studies from 2018-2022. The approach therefore aligns with the commercial trajectory of smartphone depth sensors and automotive flash LiDAR that already use standard-CMOS SPAD arrays.

If the reported jitter reduction scales to arrays without excess crosstalk, module designers could relax laser power or TDC resolution budgets, lowering cost per point. The main limitation remains the single-device test vehicle; array-level statistics and temperature dependence are still required before integration claims can be validated.

Commercial qualification cycles for automotive and consumer imaging typically run 18-24 months, so any volume impact would appear in 2027-2028 products rather than the one-year horizon suggested by some coverage.