Zen 6 Cuts Branch Mispredict Recovery to 3-3.5 ns While Doubling VNNI Throughput

Zen 6 reworks integer scheduling back to a Zen 4-style layout and allows a single thread to utilize both decode clusters introduced in Zen 5. Chips and Cheese measurements show sustained 5.96 64-bit adds per cycle versus Zen 5's 5.25, while integer multiply units drop from three to two after area-cost analysis by AMD. BTB improvements target latency over capacity, preserving Zen 5 direction-predictor accuracy but accelerating recovery.

Vector changes focus on quantized inference: 512-bit VNNI reaches 3.88 instructions per cycle against Zen 5's 1.99, and 256-bit loads now sustain four per cycle for 128 bytes total bandwidth. These shifts align with observed demand in AVX2-heavy code paths and match patterns seen in Zen 2 integer refinements that preceded broader IPC gains.

Operationally, reduced mispredict cost and doubled VNNI units lower effective latency in branch-heavy and quantized workloads without expanding FP execution width. This suggests AMD prioritized density and AI-adjacent throughput over raw FP scaling ahead of expected 2025-2026 deployments.

Next silicon will test whether the two-multiply configuration limits legacy integer code or if the L2 BTB latency trade-off appears in server traces.