FairCompressAgent Cuts VGG-11 Tensor Storage 59.54% on Fitzpatrick-17k While Raising AP to 0.5233
FairCompressAgent demonstrates an agentic loop that selects fairness-aware compression configurations for FPGA targets using measured feedback. On VGG-11 it delivers 59.54% storage reduction with simultaneous gains in accuracy and fairness. The approach replaces one-shot planning with iterative, constraint-driven refinement.
The framework composes pruning, incremental quantization, and sparse low-rank factorization behind a shared operator interface. A language-model planner reads measured profiles and enforces explicit accuracy, fairness, and storage constraints. Execution layer runs compression, fine-tuning, and constraint checks; it reports residual violations when no configuration satisfies the request. On Fitzpatrick-17k it matches one-shot search quality with 7.33 evaluations versus 12.
Measured outcomes show repeated fine-tuning stabilizes fairness metrics across requirement updates. Held-out test results confirm the selected model generalizes without additional EOpp degradation. The same workflow supports online constraint changes, demonstrating interactive refinement rather than static search.
FPGA deployment cost scales directly with tensor storage and memory bandwidth. A 59.54% reduction translates to lower on-chip memory and power draw for edge inference pipelines. When fairness constraints are enforced at selection time, downstream retraining or regulatory remediation costs fall.
Production teams can embed the measured-feedback loop into continuous integration pipelines. Thresholds on storage, AP, and EOpp become enforceable gates before hardware synthesis.
FairCompressAgent: Production FPGA deployments using the framework will exceed 50 models by Q3 2027 if average storage reduction remains above 55%.
Sources (2)
- [1]Primary Source(https://arxiv.org/abs/2609.17786)
- [2]Supporting Source(https://arxiv.org/abs/2305.18290)